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1 features ? medium-voltage and standard-voltage operation ? 2.5 (v cc = 2.5v to 5.5v) ? automotive temperature range ?40 c to 125 c ? internally organized 256 x 8 (2k) ? two-wire serial interface ? schmitt trigger, filtered inputs for noise suppression ? bidirectional data transfer protocol ? 400 khz (2.5v) compatibility ? write protect pin for hardware data protection ? 8-byte page write modes ? partial page writes are allowed ? self-timed write cycle (5 ms max) ? high-reliability ? endurance: 1 million write cycles ? data retention: 100 years ? 8-lead jedec soic and 8-lead tssop packages description the at24c02b provides 2048 bits of serial electrically erasable and programmable read-only memory (eeprom) organized as 256 words of 8 bits each. the device is optimized for use in many automotive applications where low-power and low-voltage operation are essential. the at24c02b is available in space-saving 8-lead jedec soic and 8-lead tssop packages and is acce ssed via a two-wire serial interface. in addition, the entire family is availa ble in 2.5v (2.5v to 5.5v) versions. table 1. pin configurations pin name function a0 ? a2 address inputs sda serial data scl serial clock input wp write protect nc no connect two-wire automotive temperature serial eeprom 2k (256 x 8) at24c02b preliminary 5181b?seepr?1/07 8-lead soic 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda 8-lead tssop 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda
2 at24c02b [preliminary] 5181b?seepr?1/07 figure 1. block diagram pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negat ive edge clock data out of each device. serial data (sda): the sda pin is bi-directional for serial data transfer. this pin is open-drain driven and may be wire-ored with any number of other open-drain or open- collector devices. device/page addresses (a2, a1, a0): the a2, a1 and a0 pins are device address inputs that are hard wired for the at24c02b. as many as eight 2k devices may be addressed on a single bus system (device addressing is discussed in detail under the device addressing section). write protect (wp): the at24c02b has a write protect pin that provides hard- ware data protection. the write protect pin allows normal read/write operations when absolute maximum ratings operating temperature ......................................? 55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .........................................? 65 c to +150 c voltage on any pin with respect to ground ........................................ ? 1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma
3 at24c02b [preliminary] 5181b?seepr?1/07 connected to ground (gnd). when the wr ite protect pin is connected to v cc , the write protection feature is enabled and ope rates as shown in the following table. memory organization at24c02b, 2k serial eeprom: internally organized with 32 pages of 8 bytes each, the 2k requires an 8-bit data word address for random word addressing. table 2. write protect wp pin status part of the array protected 24c02b at v cc full (2k) array at gnd normal read/write operations
4 at24c02b [preliminary] 5181b?seepr?1/07 note: 1. this parameter is characterized and is not 100% tested. note: 1. v il min and v ih max are reference only and are not tested. table 3. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +2.5v symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , a 2 , scl) 6 pf v in = 0v table 4. dc characteristics applicable over recommended operating range from: t a = ? 40 c to +125 c, v cc = +2.5v to +5.5v (unless otherwise noted) symbol parameter test condition min typ max units v cc1 supply voltage 2.5 5.5 v i cc supply current v cc = 5.0v read at 100 khz 0.4 1.0 ma i cc supply current v cc = 5.0v write at 100 khz 2.0 3.0 ma i sb1 standby current v cc = 2.5v v in = v cc or v ss 1.6 4.0 a i sb2 standby current v cc = 5.0v v in = v cc or v ss 8.0 18.0 a i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il input low level (1) ? 0.6 v cc x 0.3 v v ih input high level (1) v cc x 0.7 v cc + 0.5 v v ol2 output low level v cc = 3.0v i ol = 2.1 ma 0.4 v v ol1 output low level v cc = 1.8v i ol = 0.15 ma 0.2 v
5 at24c02b [preliminary] 5181b?seepr?1/07 notes: 1. this parameter is characterized and is not 100% tested (t a = 25 c). 2. this parameter is characterized. device operation clock and data transitions: the sda pin is normally pulled high with an exter- nal device. data on the sda pin may change only during scl low time periods (see to figure 5 on page 7). data c hanges during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (see to figure 6 on page 7). stop condition: a low-to-high transition of sda wit h scl high is a stop condition. after a read sequence, the stop command will place th e eeprom in a standby power mode (see figure 6 on page 7). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a ?0? to acknowledge that it has received each word. this happens during the ninth clock cycle. standby mode: the at24c02b features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the stop bit and the completion of any internal operations. table 5. ac characteristics applicable over recommended operating range from t a = ? 40 c to +125 c, v cc = +2.5v to +5.5v, cl = 1 ttl gate and 100 pf (unless otherwise noted) symbol parameter at24c02b units min max f scl clock frequency, scl 400 khz t low clock pulse width low 1.2 s t high clock pulse width high 0.6 s t i noise suppression time (1) 50 ns t aa clock low to data out valid 0.1 0.9 s t buf time the bus must be free before a new transmission can start (2) 1.2 s t hd.sta start hold time 0.6 s t su.sta start set-up time 0.6 s t hd.dat data in hold time 0 s t su.dat data in set-up time 100 ns t r inputs rise time (2) 300 ns t f inputs fall time (2) 300 ns t su.sto stop set-up time 0.6 s t dh data out hold time 50 ns t wr write cycle time 5 ms endurance (2) 5.0v, 25 c, page mode 1m write cycles
6 at24c02b [preliminary] 5181b?seepr?1/07 2-wire software reset: after an interruption in prot ocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: (a) create a start bit condition, (b) clock 9 cycles, (c) create an other start but followed by stop bit condition as shown below. the device is ready fo r next communication after above steps have been completed. figure 2. software reset bus timing figure 3. scl: serial clock, sda: serial data i/o scl sda 123 89 start bit start bit stop bit dummy clock cycles
7 at24c02b [preliminary] 5181b?seepr?1/07 write cycle timing figure 4. scl: serial clock, sda: serial data i/o note: 1. the writ e cycle time t wr is the time from a valid stop condition of a writ e sequence to the end of the internal clear/write cycle. figure 5. data validity figure 6. start and stop definition t wr (1) stop condition start condition wordn ack 8th bit s cl s da
8 at24c02b [preliminary] 5181b?seepr?1/07 figure 7. output acknowledge
9 at24c02b [preliminary] 5181b?seepr?1/07 device addressing the 2k eeprom device requires an 8-bit dev ice address word following a start condi- tion to enable the chip for a read or write operation (see to figure 8 on page 10). the device address word consists of a mandatory ?1?, ?0? sequence for the first four most significant bits as sh own. this is common to a ll the serial eeprom devices. the next 3 bits are the a2, a1 and a0 devi ce address bits for the 2k eeprom. these 3 bits must compare to their corresponding hardwired input pins. the eighth bit of the device address is the r ead/write operation select bit. a read opera- tion is initiated if this bit is high and a writ e operation is initiate d if this bit is low. upon a compare of the device address, th e eeprom will output a ?0?. if a compare is not made, the chip will return to a standby state. write operations byte write: a write operation requires an 8-bit data word address following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a ?0? and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will output a ?0? and the addressing device, such as a microcontroller, must terminate the writ e sequence with a stop condition. at this time the eeprom enters an internally timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete (see figure 9 on page 10). page write: the 2k eeprom is capable of an 8-byte page write. a page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the fi rst data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to seven data words. the eeprom will respond with a ?0 ? after each data word received. the microcontroller must terminate the page writ e sequence with a stop condition (see fig- ure 10 on page 11). the data word address lower three bits are in ternally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than eight data words are transmitted to the eeprom, the data word address will ?roll over? and previous data will be overwritten. acknowledge polling: once the internally timed write cycle has started and the eeprom inputs are disabl ed, acknowledge polling can be in itiated. this involves send- ing a start condition followed by the dev ice address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a ?0?, allowing the read or write se quence to continue. read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to ?1?. there are three read operations: current address read, random address read and sequential read. current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address ?roll over? during read is from the last byte of the last memory page to the first byte of the first page. the address ?roll over? du ring write is from the last byte of the cur- rent page to the first byte of the same page.
10 at24c02b [preliminary] 5181b?seepr?1/07 once the device address with the read/write se lect bit set to ?1? is clocked in and acknowl- edged by the eeprom, the curr ent address data word is se rially clocked out. the microcontroller does not respond with an input ?0? but does generate a following stop condition (see figure 11 on page 11). random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address wo rd and data word address are clocked in and acknowledged by the eeprom, the microcontr oller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. th e eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a ?0? but does generate a follow- ing stop condition (see figure 12 on page 12). sequential read: sequential reads are initiated by either a current address read or a ran- dom address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eepr om receives an ackn owledge, it will cont inue to increment the data word address and serially clock out sequential data words. when the memory address limit is reache d, the data word address will ?roll over? and the sequential read will con- tinue. the sequential read operation is terminated when the microcontroller does not respond with a ?0? but does generate a following stop condition (see figure 13 on page 12). figure 8. device address figure 9. byte write msb
11 at24c02b [preliminary] 5181b?seepr?1/07 figure 10. page write figure 11. current address read
12 at24c02b [preliminary] 5181b?seepr?1/07 figure 12. random read figure 13. sequential read
13 at24c02b [preliminary] 5181b?seepr?1/07 notes: 1. ?-b? denotes bulk. 2. ?-t? denotes tape and reel. soic = 4k per reel. tssop = 5k per reel. at24c02b ordering information ordering code package operation range at24c02bn-sp25-b (1) at24c02bn-sp25-t (2) at24c02b-tp25-b (1) at24c02b-tp25-t (2) 8s1 8s1 8a2 8a2 lead-free/halogen-free/nipdau lead finish/automotive temperature ( ? 40 c to 125 c) package type 8s1 8-lead, 0.150? wide, plastic gull wing small outline (jedec soic) 8a2 8-lead, 0.170? wide, thin shrink small outline package (tssop) options -2.5 low-voltage (2.5v to 5.5v)
14 at24c02b [preliminary] 5181b?seepr?1/07 packaging information 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
15 at24c02b [preliminary] 5181b?seepr?1/07 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances , datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e 8a2 ? tssop
16 at24c02b [preliminary] 5181b?seepr?1/07 revision history doc. rev. date comments 5181b 1/2007 added preliminary status. added new ordering information to page 12. added notes to ordering information on page 12. changed voltage from 2.7 to 2.5. deleted 8-lead pdip offering. deleted 5.0v offering. 5181a 7/2006 initial document release.
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